Jump to main content
Computer Engineering
Computer Engineering
Computer Engineering 

← Back to Research Projects

Open Innovation for RPAS (OPIRA)

Completed
DronesASEAI
Project Period 01.01.2014 – 31.03.2017
Funding BMWi
TUC Contact Prof. Dr. Dr. h.c. Wolfram Hardt

The OPIRA project (Open Innovation for RPAS) aims to investigate technological solutions for enhancing air traffic safety and the operation of RPAS (Remotely Piloted Aircraft Systems) for civil applications. The work focuses on optimizing pilot/operator assistance systems, which are to be integrated and implemented in a high-performance and cost-effective manner using modern avionics systems. The technologies will be validated under application-oriented conditions using representative simulation environments.

  

The research conducted by the Chair of Technical Computer Science focuses on developing a stereoscopic image processing pipeline on reconfigurable hardware. Electro-optical sensors, in particular, offer a wide range of applications in the field of versatile sensor technology. In aviation specifically, such systems can provide targeted support to pilots during critical situations. In safety-critical contexts, this entails meeting exceptionally high standards for system robustness and reliability. However, extracting information from high-resolution image sensors requires processing vast amounts of data in real time. General-purpose processors reach their limits in this regard. The goal of this sub-project is therefore to implement the entire stereoscopic image processing pipeline on reconfigurable hardware (FPGAs—Field Programmable Gate Arrays). This technology enables a high degree of data and functional parallelization during processing. Multiple low-level image processing approaches can be fused in an application- and situation-specific manner. The resulting outputs offer significantly enhanced information quality. Consequently, the chosen approach allows the benefits of flexible software solutions to be combined with the advantages of a high-performance, parallelizable hardware implementation.

Social Media

Connect with Us: