Professorship Circuit and System Design
Chair for Circuit and System Design

VHDL Introduction

Aim

The multi-day course (fee required) gives an introduction into the circuit design using VHDL. The course is addressed to companies and people that would like to gain/improve their design skills for FPGAs and ASICs.

Previous knowledge is not necessary, but basic user knowledge of Linux/Unix and the handling of an editor would be an advantage. At the end of the course the participants should have the ability to design, simulate, synthesize and test simple circuits (FPGAs).

Procedure

The whole course covers 3-5 days, depending on the state of knowledge and the number of participants. The practical part takes 10 to 12 hours and the theoretical part including self-study lasts approximately the same time.

We provide the material (scripts, literature) for oral presentation and private study. We also provide the computer including design software in the rooms of the chair circuit and system design.

Content

Day 1:

  • One-on-one discussion about previous knowledge, ideas and aims
  • Oral presentation "VHDL - Overview and Area of Application" and "VHDL Language and Syntax I"
  • Time for questions
  • Explanation of practical tasks, introduction into the design software (editor, simulator)
  • Time for private study (materials for oral presentation, accompanying book for the practical work, books)

Day 2:

  • Feedback, questions
  • Oral presentation "VHDL Language and Syntax II", case study ALU (approx. 1 hour)
  • Overview on material for private study: Synthesis I+II, Simulation, Project Management
  • Independent working on practical tasks (contains of 10 prepared subtasks)
  • Possibilities to call back (if needed)

Day 3 - 5 (depending on prior knowledge):

  • Independent working on practical tasks, help and explanation
  • after successfully finishing the 10 modules, they are combined to the complete system, afterwards simulation and synthesis
  • if the synthesis is successful, backannotation and timing-simulation: configuration of the FPGAs and test on hardware

Last Day:

  • Final discussion to the course (questions, feedback, discussion, outlook)

Contact

If you are interested please contact the Sekretariat.

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