Course Hardware Acceleration Using FPGAs
The challenge of the course is an intensive examination with the design steps of digital hardware as well as the efficient usage of the available hardware resources. Therefore a closer look at specific conditions in terms of synthesis for FPGA as well as for ASICs will be taken. Finally the implementation of a digital design based on a FPGA should be realized. Interdisciplinary knowledge can be acquired through extended answering of different questions, such as:
- What happens by translating the assembler code into a machine code and how do you find the used symbols in a resulting machine code?
- How is it possible to model a design environment in detail?
- How should the VHDL code be structured to create the desired hardware structure?
The course Hardware Acceleration Using FPGAs, consisting of a lecture, seminar and practice session and covers the practical use of commercial design tools. The practice covers complex design tasks based on the knowledge about design, modelling, description and synthesis of complex systems. The lecture provides the necessary theoretical knowledge about tools and algorithm.
Lecture Timeline
To get access to the lecture documents and to subscribe to the practical lab you have to subscribe for the lecture in OPAL-System as well.
- Overview Hardware
- Definition und classification of circuits
- Technology overview
- user programmable circuits
- Summary of Design heterogenous Systems (VHDL)
- System environments and testbenches
- File I/O
- Simulation Flow
- Coding Style influence
- Source Code optimization
- Synthesis of Operands
- Feedback Loops
- IF Struktures ⇔ CASE Struktures
- Synthesis attributes
- FSM Encoding
- Design-Reuse
Practice Timeline
Thursday, from 13:45 until 15:15 o'clock, with date arrangement.
Practice/Labs are held at different dates
Subscription to the lab is possible after 1st lecture in OPAL-System.
