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Professur Schaltkreis- und Systementwurf
Verification of Digital Systems
Professur Schaltkreis- und Systementwurf 

Lecture Verification of Digital Systems (0/1/2/1, SS)

The course Verification of Digital Systems (based on the winter semester course Design of Digital Systems) mainly teaches verification tools and methods for digital circuits and systems with focus on formal verification. Functionality and limits of commercial verification tools are discussed. The course consists of exercise, seminar (theory and presentation part), and a complex lab task.

Attention: Max. 60 participants! Due to limited capacity of our seminar room, the first classes will be held in hybrid form. Details are given by email.

Organization

The course Verification of Digital Systems is planned as presence course.

For course attendance and to receive updates via email, please subscribe in OPAL: Subscription to VoDS course

Please note that (for organizational reasons) we have a mixed schedule, i.e., in some cases we use seminar classes for tutorials and vice versa.

Details for tutorials, seminar classes and practice labs can be found on the other tabs of this page.

Tutorial

Please find four exercise sheets online. Access is possible after course subscription in OPAL (see "organizational" tab).

We recommend to print out the exercise sheets!

Several exercise tasks are marked with an asterisk (*). Exercise solutions must be submitted in written form (not by email!) one week after the corresponding tutorial class was given. Five out of six of these homework tasks must be solved and submitted..

Tasks marked with a double-asterisk (**) are additional tasks for your training and will not be discussed in the tutorials.

Course organization, repetition boolean algebra
08.04.2026, 9:15 - 10:45, C25.017
Tutorial - BDDs, Practice introduction
27.04.2026, 15:30 - 17:00, C22.201
Tutorial - BDDs (ctd.)
29.04.2026, 9:15 - 10:45, C25.017
Tutorial - SAT
10.06.2026, 9:15 - 10:45, C25.017
Tutorial - Temporal Logic
24.06.2026, 9:15 - 10:45, C25.017
Tutorial - Model Checking
01.07.2026, 9:15 - 10:45, C25.017
Tutorial - Coverage
08.07.2026, 9:15 - 10:45, C25.017
Exam preparation
15.07.2026, 9:15 - 10:45, C25.017

Seminar - theory part

Material: Available online

Theory - Introduction, Review, Introduction to Formal Verification
13.04.2026, 15:30 - 17:00, C22.201
Theory - Basics of Formal Verification
20.04.2026, 15:30 - 17:00, C22.201
Theory - BDDs
22.04.2026, 9:15 - 10:45, C25.017
Theory - SAT
03.06.2026, 9:15 - 10:45, C25.017
Bosch Sensortec: Advanced Verification Methods (part 2)
08.06.2026, 15:30 - 17:00, C22.201
Theory - Temporal Logic
22.06.2026, 15:30 - 17:00, C22.201
Theory - Model Checking
29.06.2026, 15:30 - 17:00, C22.201
Theory - Coverage
06.07.2026, 15:30 - 17:00, C22.201

Seminar - presentation part

Seminar attendance is compulsory!

Seminar introduction
15.04.2026, 9:15 - 10:45, C25.017
Student presentations - 1
04.05.2026, 15:30 - 17:00, C22.201
Student presentations - 2
06.05.2026, 9:15 - 10:45, C25.017
Student presentations - 3
11.05.2026, 15:30 - 17:00, C22.201
Student presentations - 4
13.05.2026, 9:15 - 10:45, C25.017
Student presentations - 5
18.05.2026, 15:30 - 17:00, C22.201
Student presentations - 6
20.05.2026, 9:15 - 10:45, C25.017
Student presentations - 7
27.05.2026, 9:15 - 10:45, C25.017
Student presentations - 8
01.06.2026, 15:30 - 17:00, C22.201

Practice labs

Practice tasks are to be solved at home, there is no compulsory attendance. The lab schedule given in the official timetable is to be neglected, as our lab room has no adequate capacity for everyone. Please make individual appointments for lab consultation (live or by videochat/Zoom).

For lab material access, please subscribe in OPAL.

Material: online.

In addition to the lab task, you also have to solve the homework exercise tasks marked with an asterisk (*) (precondition for exam)!

Deadline for lab tasks is 22.06.

Note: The lab tasks are introduced in the tutorials.

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