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Professur Schaltkreis- und Systementwurf
Design of Digital Systems

Course Design of Digital Systems (WS)

The course Design of Digital Systems is based on the knowledge acquired from lectures of circuit and system design. Focus of this course is on design, modeling, description and synthesis of complex systems by using commercial design tools. The course consists of lecture, exercise, practice sessions and a seminar.

Recommended Literature

  • Peter J. Ashenden, "The Designer's Guide to VHDL, 3rd Edition", 2008, ISBN 978-0-12-088785-9
  • Janick Bergeron, "Writing Testbenches: Functional Verification of HDL Models", Springer; Auflage: 2nd ed. 2003, ISBN 978-1402074011
  • Black, David C. and Donovan, Jack SystemC: From the ground up. Kluwer Academic. 2004.
  • High-Level Synthesis Blue Book. Michael Fingeroff

 - EET (free online available)
  • High-Level-Synthesis - Introduction to Chip and System Design. D.D. Gajski, Kluwer Publishers, 1992
  • Fundamentals of solid-state electronics. Chih-Tang Sah, ISBN 978-9810206376

Organization

For course attendance and to receive updates via email, please subscribe in OPAL: Subscription to DoDS course

Details for lectures, tutorials, practice labs and seminar can be found on the other tabs of this page.

Lecture Organization

The course is planned on-site in classroom. Additionally, we provide lecture material (slides). The access link is available in OPAL after subscription.

Lecture Material

  • is available in OPAL. To gain access, a subscription is necessary ("Subscription to DoDS course").

Schedule

Lecture: Introduction
16.10.2023, 13:45 - 15:15, room C10.111 Attention: Seminar slot
Lecture: Specification
20.10.2023, 11:30 - 13:00, room C25.014
Lecture: SystemC
03.11.2023, 11:30 - 13:00, room C25.014
Lecture: VHDL
17.11.2023, 11:30 - 13:00, room C25.014
Lecture: HLS
01.12.2023, 11:30 - 13:00, room C25.014
Lecture: Simulation I
15.12.2023, 11:30 - 13:00, room C25.014
Lecture: Simulation II
19.01.2024, 11:30 - 13:00, room C25.014

Exercise Organization

Exercises are given on-site in the lecture room. Before attending an exercise, it is necessary to work through the lecture material of that topic.

Exercise Materials

  • Please subscribe to the DoDS exercise here: OPAL
  • After subscription, the course documents can be accessed using the "Documents" in OPAL in the left navigation bar.

Schedule

Exercise 1: Specification
27.10.2023, 11:30 - 13:00, room C25.014
Exercise 2: SystemC
13.11.2023, 13:45 - 15:15, room C22.201. Attention: Seminar slot!
Exercise 3: VHDL
24.11.2023, 11:30 - 13:00, room C25.014
Exercise 4: HLS
08.12.2023, 11:30 - 13:00, room C25.014
Exercise 5: Simulation I
12.01.2024, 11:30 - 13:00, room C25.014
Exercise 6: Simulation II
26.01.2024, 11:30 - 13:00, room C25.014
Exercise 7: Consultation/exam preparation
02.02.2024, 11:30 - 13:00, room C25.014

Information for practice labs

All lab tasks have to be done at home via remote access to our servers. This procedure will be explained in the first exercise unit. Additionally, it is possible to work on-site in our lab rooms on request.

Be sure to attend our lab introduction class (see schedule below) as we explain login procedure and other organizational things.

It is possible to get individual consultation on the lab tasks. Please contact us using the Email feature in OPAL in case.

To pass one lab task, you have to submit:

  • the preparation tasks as well as
  • the lab solution.
Please submit to the individual supervisor (see task sheets).

Deadline is 15.01.2024. Submit earlier for individual feedback and a second chance in case of there are major problems in your solution.

Schedule

Lab introduction
10.11.2023, 11:30 - 13:00, room C25.014

Seminar information

Seminar introduction and topic assignment take place in the seminar slot on 17.10., 1.45pm, which will be our first seminar session. The seminar is held on-site and additionally streamed via Zoom (access link available via OPAL after subscription). During this seminar session, the upcoming seminar schedule will be discussed.

Schedule

Seminar introduction
06.11.2023, 13:45 - 15:15, room C10.111
Power optimization techniques, Fundamental design structures on Register Transfer Level, Structure of an Arithmetic Logical Unit
11.12.2023, 13:45 - 15:15, room C10.111
Structure of an Arithmetic Logical Unit, Survey on recent High-Level-Synthesis tools, Survey on Hardware acceleration
18.12.2023, 13:45 - 15:15, room C10.111
Structure of an Arithmetic Logical Unit, Survey on Hardware acceleration, Programmable Hardware – An Overview
08.01.2024, 13:45 - 15:15, room C10.111
Programmable Hardware – better than ASICs?, Minimizing Crosstalk, The importance of verification
15.01.2024, 13:45 - 15:15, room C10.111
The importance of verification, About the importance of timing analysis in synchronous digital system design, Speech Recognition and Language Processing
22.01.2024, 13:45 - 15:15, room C10.111
IC manufacturing, Moore's law
29.01.2024, 13:45 - 15:15, room C10.111