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Professur Schaltkreis- und Systementwurf
Design of Digital Systems
Professur Schaltkreis- und Systementwurf 

Course Design of Digital Systems (WS)

The course Design of Digital Systems is based on the knowledge acquired from lectures of circuit and system design. Focus of this course is on design, modeling, description and synthesis of complex systems by using commercial design tools. The course consists of lecture, exercise, practice sessions and a seminar.

Recommended Literature

  • Peter J. Ashenden, "The Designer's Guide to VHDL, 3rd Edition", 2008, ISBN 978-0-12-088785-9
  • Janick Bergeron, "Writing Testbenches: Functional Verification of HDL Models", Springer; Auflage: 2nd ed. 2003, ISBN 978-1402074011
  • Black, David C. and Donovan, Jack SystemC: From the ground up. Kluwer Academic. 2004.
  • High-Level Synthesis Blue Book. Michael Fingeroff

 - EET (free online available)
  • High-Level-Synthesis - Introduction to Chip and System Design. D.D. Gajski, Kluwer Publishers, 1992
  • Fundamentals of solid-state electronics. Chih-Tang Sah, ISBN 978-9810206376

Organization

For course attendance and to receive updates via email, please subscribe in OPAL: Subscription to DoDS course

Details for lectures, tutorials, practice labs and seminar can be found on the other tabs of this page.

Lecture Organization

The course is planned on-site in classroom. Additionally, we provide lecture material (slides). The access link is available in OPAL after subscription.

Lecture Material

  • is available in OPAL. To gain access, a subscription is necessary ("Subscription to DoDS course").

Schedule

Lecture: Introduction
17.10.2025, 09:15 - 10:45, online (Zoom link is sent to OPAL group beforehand)
Lecture: Specification
24.10.2025, 09:15 - 10:45, room C10.112
Lecture: SystemC
14.11.2025, 09:15 - 10:45, room C10.112
Lecture: VHDL
21.11.2025, 09:15 - 10:45, room C10.112
Lecture: HLS
12.12.2025, 09:15 - 10:45, room C10.112
Lecture: Simulation I
09.01.2026, 09:15 - 10:45, room C10.112
Lecture: Simulation II
23.01.2026, 09:15 - 10:45, room C10.112

Exercise Organization

Exercises are given on-site in the lecture room. Before attending an exercise, it is necessary to work through the lecture material of that topic.

Exercise Materials

  • Please subscribe to the DoDS exercise here: OPAL
  • After subscription, the course documents can be accessed using the "Documents" in OPAL in the left navigation bar.

Schedule

Exercise 1: Specification
07.11.2025, 09:15 - 10:45, room C10.112
Exercise 2: SystemC
28.11.2025, 09:15 - 10:45, room C10.112
Exercise 3: VHDL
05.12.2025, 09:15 - 10:45, room C10.112
Exercise 4: HLS
19.12.2025, 09:15 - 10:45, room C10.112
Exercise 5: Simulation I
16.01.2026, 09:15 - 10:45, room C10.112
Exercise 6: Simulation II
30.01.2026, 09:15 - 10:45, room C10.112
Exercise 7: Consultation/exam preparation
06.02.2026, 09:15 - 10:45, room C10.112

Information for practice labs

All lab tasks have to be done at home via remote access to our servers. This procedure will be explained in the lab introduction class. Additionally, it is possible to work on-site in our lab rooms (on request only). It is possible to get individual consultation on the lab tasks. Please contact us using the Email feature in OPAL in case.

Be sure to attend our lab introduction class (see schedule below) as we explain login procedure and other organizational things.

To pass one lab task, you have to submit:

  • the preparation tasks as well as
  • the lab solution.
Please submit to the individual supervisor (see task sheets).

Each lab has an own deadline - see OPAL for details. Submit earlier for individual feedback and a second chance in case of there are major problems with your solution.

Schedule

Specification, lab introduction
13.11.2025, 15:30 - 17:00, room C10.012

Seminar information

Please note that seminar organization has changed (compared to last years). Please visit introduction lecture and exercise for more information. Please find planned classes below:

Schedule

Specification, lab introduction
13.11.2025, 15:30 - 17:00, room C10.012
The beauty of IC design (by Bosch Sensortec Dresden)
20.11.2025, 15:30 - 17:00, room C10.012
SystemC and VHDL
04.12.2025, 15:30 - 17:00, room C10.012
HLS
08.01.2026, 15:30 - 17:00, room C10.012
Advanced Verification Methods (by Bosch Sensortec Dresden)
15.01.2026, 15:30 - 17:00, room C10.012
IC Test and Virtual Test (by Advantest Europe) (invited)
29.01.2026, 15:30 - 17:00, room C10.012
Simulation
05.02.2026, 15:30 - 17:00, room C10.012