Using XML in VHDL Analysis and Simulation

Karayiannis | Mades | André Windisch | Schneider | Wolfgang Ecker

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September 2000

Typ	InProceedings
Quelle	Proceedings of the Forum on Design Languages (FDL) S. 117 - 122
Adresse	Tuebingen, Germany
ISBN	3-0000-6540-7
Zusatz	SIG-VHDL & ECS
Bibtex	Anzeigen @InProceedings{KaMaAnWiScWoEc00,      address      = {Tuebingen, Germany},      author       = {Karayiannis, Mades, André Windisch, Schneider, Wolfgang Ecker},      title        = {Using XML in VHDL Analysis and Simulation},      note         = {SIG-VHDL & ECS},      pages        = {117--122},      month        = {September},      year         = {2000},      isbn         = {3-0000-6540-7},      booktitle    = {Proceedings of the Forum on Design Languages (FDL)}, }