VHDL-Beschreibungen von Zahlenformatkonvertierungen
Der Code ist frei verfügbar. Es wird jedoch keine Gewähr für fehlerfreie Funktionalität, Support und Updates gegeben.
| Name | Download | Beschreibung | Simulation | ASIC |
|---|---|---|---|---|
| Float32toUnsigned.vhd | Converts a Float32 (IEEE754 Single) to Integer (Unsigned); synthesizable VHDL description; input/output as std_logic_vector |
 |
|
|
| Float32toSigned.vhd |
Converts a Float32 (IEEE754 Single) to Integer (Signed); synthesizable VHDL description; input/output as std_logic_vector |
|
|
|
| UnsignedtoFloat32.vhd |
Converts an Integer (Unsigned) to Float32 (IEEE754 Single); synthesizable VHDL description; input/output as std_logic_vector |
|
|
|
| SignedtoFloat32.vhd |
Converts an Integer (Signed) to Float32 (IEEE754 Single); synthesizable VHDL description; input/output as std_logic_vector |
|
|
