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Professur Elektronische Bauelemente der Mikro- und Nanotechnik
Professur Elektronische Bauelemente der Mikro- und Nanotechnik

Course Integrated Circuit Design - Transistor Level



The enrollment will be effected on the OPAL platform, where you'll find further informations about the course.

Course Content

Lecture Complexes
  1. Specifics of Integrated Circuits
  2. Digital elementary Circuits in MOS- and CMOS-Technology
    • Inverter in MOS-Technology (Analysis, Design)
    • Inverter in CMOS-Technology (Analysis, Design)
    • Logic Design with Transmission Gates (Transfer characteristic, resistive characteristic, dynamic behavior)
    • Circuit Interconnections (Input Stages, Output Stages)
    • Array and Split Structures
    • C²MOS Technique
    • Differential CMOS Logic
    • Schmitt Trigger as special Comparator Circuit
  3. Digital Bipolar Circuits
    • Emitter Coupled Logic
    • Current Mode Logic (CML)
  4. Digital BiCMOS Circuits
    • Elementary Circuitry
    • Rail to Rail BiCMOS Circuits
    • BiCMOS Logic
  5. Dynamic MOS Circuits
    • Pseudo NMOS-Technique
    • DOMINO CMOS Logic
    • No-Race-Logic (NORA-Logic)
    • Dynamic Current Mode Logic (DyCML)
  6. Analog Elementary Circuits
    • Current Sources - Current Mirror
    • Voltage Sources
    • Amplifier
  7. Special Circuits
    • DRAM Read-out Amplifier
    • Oscillators
Exercise Complexes
  1. Analysis of inverters
  2. Dimensioning of MOS inverters and gates, transfer characteristic of different logic families
  3. Analysis and dimensioning of CMOS circuits
  4. Analysis and dimensioning of ECL circuits
  5. Analysis and dimensioning of voltage sources
  6. Design of combinational and sequential circuits
  7. Function analysis of CMOS and BiCMOS gates
  8. Output stages, ring oscillators and DRAM readout amplifiers
Practical Training
  • Complex Lab
    • Dimensioning and electric simulation of a simple circuitry
    • Transformation into layout respecting given design rules
    • Network extraction and comparison (LVS)
    • Optional extraction of parasitic capacitances (PEX)

Degree Programs

  • Compulsory Elective Subject in the 2nd Semester of the Master Course Micro and Nano Systems (M_MN__2)

  • Compulsory Elective Subject in the 2nd Semester of the Master Course Computational Science (M_CS__2)

Timetable for the current Semester

TypeWeekdayGroupsTimeRoomStart
Lon ThursdaysM_MN1_2, M_MN2_2, M_CS__213.45-15.152/NK0032024-04-04
Eon Tuesdays, 1st weekM_MN1_2, M_MN2_2, M_CS__209.15-10.452/D2212024-04-09
Pon WednesdaysM_MN1_2, M_MN2_2, M_CS__207.30-10.452/W3682024-04-24

Examination current Semester (catch up and repeat)

Date / Time:individually
Room:2/W366 (new: C25.366)
Type:Oral examination, every 30 min
Examiner:M.Sc. Beyer
Observer:DI Loebel