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InProceedings

Wolfram Hardt and Bernd Kleinjohann
Achitecture Level Optimization for Asynchronous IPs
IN Proceedings of 13th Annual IEEE International ASIC/SOC Conference, IEEE Computer Society, September 2000. ISBN: 0-7803-6598-4

Schneider and Mades and André Windisch and Manfred Glesner and Wolfgang Ecker
Anatomy of a VHDL-AMS Environment.
IN Proceedings of the Forum on Design Languages (FDL), page 159 - 165, September 2000. ISBN: 3-0000-6540-7

André Windisch and Schneider and Mades and Dieter Monjau and Wolfgang Ecker
A VHDL-Centric Mixed-Language Simulation Environment
IN Proceedings of the Forum on Design Languages (FDL), page 339 - 345, September 2000. ISBN: 3-0000-6540-7

Karayiannis and Mades and André Windisch and Schneider and Wolfgang Ecker
Using XML in VHDL Analysis and Simulation
IN Proceedings of the Forum on Design Languages (FDL), page 117 - 122, September 2000. ISBN: 3-0000-6540-7

Schneider and André Windisch and Mades and Manfred Glesner and Dieter Monjau and Wolfgang Ecker
A System-Level Simulation Environment for System-On-Chip Design
IN Proceedings of 13th Annual IEEE International ASIC/SOC Conference, page 58 - 62, September 2000. ISBN: 0-7803-6598-4