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InProceedings
2001
Mathias Sporer and Tobias Weber and Dieter Monjau
Anwendung von UML zur Beschreibung von eingebetteten Systemen
IN 4. GI/ITG/GMM Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, page 75 - 86, Verlag MoPress, Pohrsdorf, February 2001. ISBN: 3-00-007440-6
Anwendung von UML zur Beschreibung von eingebetteten Systemen
IN 4. GI/ITG/GMM Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, page 75 - 86, Verlag MoPress, Pohrsdorf, February 2001. ISBN: 3-00-007440-6
Markus Deppe and Michael Robrecht and Mauro Zanella and Wolfram Hardt
Rapid Prototyping of Real-Time Control Laws for Complex Mechatronic Systems
IN Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping, IEEE Computer Society, 2001.
Rapid Prototyping of Real-Time Control Laws for Complex Mechatronic Systems
IN Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping, IEEE Computer Society, 2001.
2000
Schneider and Mades and Manfred Glesner and André Windisch and Wolfgang Ecker
An Open VHDL-AMS Simulation Framework
IN IEEE/ACM International Workshop on Behavioral Modeling and Simulation (BMAS 2000), page 89 - 94, IEEE Computer Society, October 2000. ISBN: 0-7695-0893-6
An Open VHDL-AMS Simulation Framework
IN IEEE/ACM International Workshop on Behavioral Modeling and Simulation (BMAS 2000), page 89 - 94, IEEE Computer Society, October 2000. ISBN: 0-7695-0893-6
Karayiannis and Mades and André Windisch and Schneider and Wolfgang Ecker
Using XML for Represantation and Visualization of Elaborated VHDL-AMS Models
IN Proceedings of the VHDL International Users Forum (VIUF), page 83 - 87, IEEE Computer Society, October 2000. ISBN: 0-7695-0890-1
Using XML for Represantation and Visualization of Elaborated VHDL-AMS Models
IN Proceedings of the VHDL International Users Forum (VIUF), page 83 - 87, IEEE Computer Society, October 2000. ISBN: 0-7695-0890-1
Wolfgang Ecker and André Windisch and Mades and Schneider and Yang
Gated Clocks in RT-Synthesis and Simulation
IN Proceedings of the VHDL International Users Forum (VIUF), page 59 - 63, IEEE Computer Society, October 2000. ISBN: 0-7695-0890-1
Gated Clocks in RT-Synthesis and Simulation
IN Proceedings of the VHDL International Users Forum (VIUF), page 59 - 63, IEEE Computer Society, October 2000. ISBN: 0-7695-0890-1
Wolfram Hardt and Bernd Kleinjohann
Achitecture Level Optimization for Asynchronous IPs
IN Proceedings of 13th Annual IEEE International ASIC/SOC Conference, IEEE Computer Society, September 2000. ISBN: 0-7803-6598-4
Achitecture Level Optimization for Asynchronous IPs
IN Proceedings of 13th Annual IEEE International ASIC/SOC Conference, IEEE Computer Society, September 2000. ISBN: 0-7803-6598-4
Schneider and Mades and André Windisch and Manfred Glesner and Wolfgang Ecker
Anatomy of a VHDL-AMS Environment.
IN Proceedings of the Forum on Design Languages (FDL), page 159 - 165, September 2000. ISBN: 3-0000-6540-7
Anatomy of a VHDL-AMS Environment.
IN Proceedings of the Forum on Design Languages (FDL), page 159 - 165, September 2000. ISBN: 3-0000-6540-7
André Windisch and Schneider and Mades and Dieter Monjau and Wolfgang Ecker
A VHDL-Centric Mixed-Language Simulation Environment
IN Proceedings of the Forum on Design Languages (FDL), page 339 - 345, September 2000. ISBN: 3-0000-6540-7
A VHDL-Centric Mixed-Language Simulation Environment
IN Proceedings of the Forum on Design Languages (FDL), page 339 - 345, September 2000. ISBN: 3-0000-6540-7
Karayiannis and Mades and André Windisch and Schneider and Wolfgang Ecker
Using XML in VHDL Analysis and Simulation
IN Proceedings of the Forum on Design Languages (FDL), page 117 - 122, September 2000. ISBN: 3-0000-6540-7
Using XML in VHDL Analysis and Simulation
IN Proceedings of the Forum on Design Languages (FDL), page 117 - 122, September 2000. ISBN: 3-0000-6540-7
Schneider and André Windisch and Mades and Manfred Glesner and Dieter Monjau and Wolfgang Ecker
A System-Level Simulation Environment for System-On-Chip Design
IN Proceedings of 13th Annual IEEE International ASIC/SOC Conference, page 58 - 62, September 2000. ISBN: 0-7803-6598-4
A System-Level Simulation Environment for System-On-Chip Design
IN Proceedings of 13th Annual IEEE International ASIC/SOC Conference, page 58 - 62, September 2000. ISBN: 0-7803-6598-4
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