file_declaration ::= |
|||
identifier_list ::= identifier { , identifier }
subtype_indication ::=
[
resolution_function_
name ] type_mark [ constraint ]
file_open_information ::=
[
open
file_open_kind_
expression ] is file_logical_name
File declarations are incompatible between VHDL'87 and VHDL'93!
The standard does not define what happens if more than one logical files access the same physical file, specifically for different access modes.