3.11 STEP 10: The Camera

3.11.1 Synopsis

Now all submodules must be merged into one design, the complete camera controller. So all modules have to be connected on a new level of hierarchy. This is called structural modelling.

Structural modelling means the use (instantiation) and wiring of components resulting in a net list. VHDL provides the following means for structural modelling:

Before you can use an object in VHDL you have to declare it. As in VHDL'87 only components can be instantiated these have to be declared first. This is done in the declarative part of an architecture or within a package which then has to be referenced.

The actual instantiation is the integration and wiring of the component. The component configuration determines which entity has to be used for a specific component instantiation. If the name of the component instantiated and the name of the entity to be used are identical (mandatory for synthesis!) then no specific component configuration has to be given.

The interface of the top module is shown in the following picture:

 

The interface of the top module

 

3.11.2 Implementation

Part of the VHDL code of the camera

library ieee;
use ieee.std_logic_1164.all;
use work.P_DISPLAY.all;
entity CAMERA is
  port( CLK     : in  std_ulogic;
        RESET   : in  std_ulogic;
        TRIGGER : in  std_ulogic;
        SWITCH  : in  std_ulogic;
        KEYPAD  : in  std_ulogic_vector
                           (9 downto 0);
        MOTOR_READY : in     std_ulogic;
        EXPOSE  : buffer std_ulogic;
        DISPLAY : out T_DISPLAY);
end CAMERA;
 
  • The top entity contains the ports
    which will be later connected to
    pads. So these pads can be con-
    nected with the corresponding
    wires in the camera.
architecture STRUCT of CAMERA is

  component DISP_DRV
    port(···);
  end component;
  component DECODER
    port (···);
  end component;
  component EXP_FF
    port(···);
  end component;
  component DISP_CTRL
    port(···); 
  end component;
  component MOTOR_TIMER
    port(···); 
  end component;
  component EXP_CTRL
    port(···);
  end component;
  component MAIN_CTRL
    port(···); 
  end component;

  signal W_KEY         : T_DIGITS;
  signal W_NO_PICS     : T_DIGITS;
  signal W_EXP_TIME    : T_DIGITS;
  signal W_SHOW_TIME   : std_ulogic;
  signal W_TIMER_GO    : std_ulogic;
  signal W_MOTOR_GO    : std_ulogic;
  signal W_MOTOR_ERROR : std_ulogic;
  signal W_ERROR       : std_ulogic;
  
begin
  U_DISP_DRV  : DISP_DRV  port map(···);
  U_DECODER   : DECODER   port map(···);
  U_EXP_FF    : EXP_FF    port map(···);
  U_DISP_CTRL : DISP_CTRL port map(···);
  U_MOTOR_TIMER : MOTOR_TIMER port map(···);
  U_EXP_CTRL  : EXP_CTRL  port map(···);
  U_MAIN_CTRL : MAIN_CTRL port map(···);
end STRUCT;
           
  • As this is the top architecture all
    entitities modelled so far have to
    be included. Therefore they are
    declared as components in the
    architecture.
                             
  • All internal signals have to be
    declared.
   
  • Here all the components are
    instantiated and connected to the
    appropriate signals.
       
configuration CFG_CAMERA of CAMERA is
  for STRUCT
    for all : DECODER
      use entity work.DECODER(RTL_CASE);
    end for;
  end for;
end CFG_CAMERA;
  • As there are two architectures for
    the decoder a configuration is
    written. This configuration selects
    the architecture RTL_CASE.