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The USE -statement can also be placed as a context-statement in front of every library module such as entity, architecture, package, package body and configuration.
Overloading is defined for subprograms, operators and values of enumeration types. Overloading is the simultaneous visibility of several subprograms, operators or of object values which have the same name and may belong to different enumeration types. By using overloading it is possible to extend a function's range of application. The several variants of a subprogram or an operator only differ in the type and number of their arguments and results. VHDL-programs recognise from the context (i.e. from the number and types of arguments) which of the visible variants is to be used. If a definite decision is not possible, i.e. if several visible alternative prove to be ``suitable`` for the required task an error is reported. With the concept of overloading, VHDL-models become easier to survey as it is not necessary to name a new designator for every variant of a certain functionality.