In order to follow the exercises you will need an editor to enter the code. It is advisable to use an editor with a VHDL language mode as they facilitate the detection of typographic errors in VHDL keywords. The notorious Emacs disposes of a powerful VHDL macro set with templates for most language constructs, special copy & paste functions for signal lists and much more.
As the VHDL simulators can not deal with ASCII text immediately, your designs need to be compiled into a machine readable format first. After the proper behaviour has been verified, a synthesis tool is used to map the RTL description to a network of gates. In addition to the software package you will also need a library containing a description of the properties of all available cells.
The goal of this pre-exercise is to get used to the simulation and synthesis tools, and to learn the basic commands of the tools used. As there is a great variety of tools we can give only very generally descriptions of the tasks to do. This exercise does not require any specific VHDL knowledge. In order to get used to the tools, please refer to the corresponding user manuals of the software tools used and proceed through the following steps:
First, you will need a directory where you can store the VHDL source code files. In the following, we assume that ~/workshop is the base directory for this project. It is advisable to separate the VHDL sources from their derived files, i.e. we will create a subdirectory ~/workshop/WORK for the analysed objects.