2.5 Package declaration

...
ENTITY e IS
    ...
BEGIN
    ...
END e ;

...
ARCHITECTURE a OF e IS
    ...
BEGIN
    ...
END a ;

...
CONFIGURATION c
        OF e IS
    ...
    ...
    ...
END


...
PACKAGE pkg IS
    ...
    ...
    ...
END pkg ;

package declaration ::=

package
identifier is
    package_declarative_part
end [ package ] [ package _simple_name ] ;


..
PACKAGE BODY pck
        IS
    ...
    ...
    ...
END pck ;

...
b: BLOCK IS
    ...
BEGIN
    ...
END BLOCK b ;

FUNCTION f (...)
    RETURN r IS
    ...
BEGIN
    ...
END f ;

PROCEDURE p (...) IS
    ...
BEGIN
    ...
END p ;

p : PROCESS
    ...
BEGIN
    ...
END PROCESS p ;

2.5.1 Further definitions

identifier ::=
    basic_identifier | extended_identifier

package_declarative_part ::=
    { package_declarative_item }

simple_name ::= identifier

2.5.2 Examples

PACKAGE pck IS
   CONSTANT CINT : integer;
END pck;

Declaration of the package pck in which
the integer constant CINT is declared.

PACKAGE tristate IS
   TYPE Tri IS ('0', '1', 'Z', 'E');
   FUNCTION BitVal (Value : Tri)
      RETURN Bit;
   FUNCTION TriVal (Value : Bit)
      RETURN Tri;
   TYPE TriVector IS ARRAY (
      NATURAL RANGE <>) OF Tri;
   FUNCTION Resolve (Sources : TriVector)
      RETURN Tri;
END tristate;

Declaration of the package tristate in which
the enumeration type Tri and three functions
( BitVal , TriVal , Resolve ) with the corresponding
transfer values and result types are declared.
Apart from that a type TriVector is declared
as a vector of the type Tri and the maximum
length ( NATURAL RANGE <> ).

PACKAGE pck_2 IS
   USE
work.parts.all;
   SIGNAL S : resol_bit BUS := '1';
   DISCONNECT S AFTER 2 ns;
   COMPONENT latch
      GENERIC (C : Natural);
      PORT (A : IN Bit;
            B : OUT Bit_vector (1 TO C));
   END COMPONENT ;
   COMPONENT clock
      PORT (CK : OUT Bit);
   END COMPONENT ;
END pck_2;

The objects from the library parts are integrated.

The signal S is declared as a guarded signa l (BUS)
and initialized with the value 1.
The driver(s) for the signal S is/are
not separated immediately after S has been
deactivated but only 2 ns afterwards.

The two components latch and clock with the
corresponding in- and outputs are declared.
The component latch also contains a Generic N .