2.6 VHDL Synthesis
After you have verified the function of your model with the simulator you can run the synthesis tool. Again you have to analyse the VHDL source code. This is normally done automatically when you read in your VHDL file.
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Read the file "and_gate.vhd" (via File -> Read). Go through the tool messages to check whether your design is conform to the synthesis subset which is supported by your synthesis tool. In general only a subset of the 1076-VHDL standards is supported. This subset is now (end of 1999) standardized but not supported by the tools until now.
In future tasks/exercises we will define our own packages. The synthesis tool requires that packages are read (analysed) before they are used or referenced. The most frequent errors with the synthesis are missing not read (analysed) packages!
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Sometimes you can examine your design after you have read in the source file. This representation is called generic netlist. (Translation of the VHDL code in a set of tool specific symbolic gates).
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The most tools are optimizing for area if no specific synthesis constraints are set. Use the defaults constraint settings and start the design optimization (the actual synthesis; refer to your user manual).
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You will now get a netlist which is optimized for the selected target library (see Synthesis Setup).
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Examine the gate level implementation. Normally commands for zooming in and out, features for highlighting special paths, analysis functions and report generators are available.
The report of the area (ASIC) needed or percent of available resources (FPGA) used, the maximum clock frequency possible and sometimes an estimation of the power consumption are interesting reports.