1. Introduction
This VHDL teaching program is divided into several exercises. By writing typical VHDL programs you learn how to use this hardware description language. In the beginning you are guided in a step by step manner, later on when you are used to the language and the tools you will solve the tasks on your own. We are referring to the VHDL'87 standard, because the VHDL'93 is not yet supported by all tool manufacturers.
1.1 Structure of the Exercises
The tasks are divided into different sections:
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Synopsis:
In this section you learn about the goal of the task and the function of the model within the whole design.
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Behaviour:
This section tells you more about the function of the model.
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Data Types:
In this section the types to be used in the current exercise are described.
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To Do:
Here is the precise description of your job to solve the task.
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Implementation:
Here you find a list of VHDL code which represents a possible implementation.
1.2 Style Guide
In VHDL it is very important to have a consistent naming. The following naming conventions should be followed within this workshop:
Naming conventions
File name:
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mydesign.vhd
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for the VHDL file
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Entity name:
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MYDESIGN
TB_MYDESIGN
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for the model
for the testbench
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Architecture name:
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RTL
TEST
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for RTL code
for the architecture of the testbench
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Configuration name:
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CFG_TB_MYDESIGN
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for the configuration of the testbench
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Type definition name:
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T_<TYPE_NAME>
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a leading T_ ...
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