2.5 VHDL Simulator

In order to verify the proper behaviour of your VHDL code, you will also need to create testbenches that stimulate your design. The testbench for the AND gate contains the instantiation of the device under test (DUT) and a simple stimulus process that assigns all possible signal combinations to the component inputs.

Please create the file tb_and_gate.vhd and enter the following VHDL code:

 

VHDL code of the testbench

library IEEE;
use IEEE.std_logic_1164.all;

entity TB_AND_GATE is
end TB_AND_GATE;



architecture TEST of TB_AND_GATE is
   component AND_GATE
      port (A, B : in  std_logic;
            Z    : out std_logic);
   end component;

   signal W_A, W_B, W_Z : std_logic;
begin

   DUT : AND_GATE
      port map(A => W_A,
               B => W_B,
               Z => W_Z);
   STIMULI : process
   begin
      W_A <= '0';
      W_B <= '0';
      wait for 10 ns;

      W_A <= '1';
      wait for 10 ns;

      W_B <= '1';
      wait for 10 ns;

      W_B <= '0';
      wait for 10 ns;

      wait;
   end process STIMULI;
end TEST;

configuration CFG_TB_AND_GATE of
                   B_AND_GATE is
   for TEST
   end for;
end CFG_TB_AND_GATE;

 

Prior to simulation you will also have to compile the file, i.e. please run the VHDL analyser (e.g. 'myanalyser and_gate.vhd'; or you have to select a menu entry, e.g. 'analyse').

Now you are ready to invoke the VHDL simulator if not already done. If not done automatically you have to choose the object to simulate and specify additional simulation parameters. Remember that the configuration is the only VHDL object that can be simulated. Some tools require no (top-) configuration as they built up a default configuration on their own. In this case you can select the top entity for simulation (here it would be TB_AND_GATE). In the other case please select CFG_TB_AND_GATE and press OK to open the simulation control window. The next points describe features which are common to most simulation tools: