3. exercises

3.1 STEP 1: A Multiplexer

3.1.1 Synopsis

Your first task is to write the VHDL description of a multiplexer. The camera display shall either show the number of pictures that have already been taken or the current exposure time. The following figure shows a schematic of the multiplexer:

 

The Multiplexer

 

3.1.2 Implementation

Implementation of the multiplexer

library ieee;
use ieee.std_logic_1164.all;

entity DISP_MUX is
  port(EXP_TIME     : in  integer;
       NO_PICS      : in  integer;
       SHOW_TIME    : in  std_ulogic;
       DISP_PHOTO   : out integer);
end DISP_MUX;

architecture RTL of DISP_MUX is
begin
  process(SHOW_TIME, NO_PICS, EXP_TIME)
  begin
    if SHOW_TIME = '1' then
      DISP_PHOTO <= EXP_TIME;
    else
      DISP_PHOTO <= NO_PICS;
    end if;
  end process;
end RTL;
  • As the std_ulogic data type is used
    for the control signal SHOW, the
    std_logic_1164 package needs to
    be referenced. It is located in the
    IEEE library.
  • Interface definition according to
    the specification.
  • As the VHDL code shall be synthe-
    sized, the architecture is called RTL.
  • The multiplexing algorithm is
    implemented as a process with
    sensitivity list. All signals which
    are read in the process have to be
    listed in order to obtain the same
    behaviour on RT- andgate-level.
  • An if-construct always results in a
    multiplexer
 

Testbench for the DISP_MUX module

library ieee;
use ieee.std_logic_1164.all;

entity TB_DISP_MUX is
end TB_DISP_MUX;


architecture TEST of TB_DISP_MUX is
  component DISP_MUX
    port(EXP_TIME   : in integer;
         NO_PICS    : in integer;
         SHOW_TIME  : in std_ulogic;
         DISP_PHOTO : out integer);
  end component;

  signal W_EXP_TIME   : integer    := 0;
  signal W_NO_PICS    : integer    := 0;
  signal W_SHOW_TIME  : std_ulogic := '0';
  signal W_DISP_PHOTO : integer;
begin               -- architecture
  DUT : DISP_MUX
    port map (
      EXP_TIME   => W_EXP_TIME,
      NO_PICS    => W_NO_PICS,
      SHOW_TIME  => W_SHOW_TIME,
      DISP_PHOTO => W_DISP_PHOTO);

  STIMULI : process
  begin
    wait for 30 ns;
    W_NO_PICS  <= 2;
    W_EXP_TIME <= 64;
    wait for 20 ns;
    W_NO_PICS <= 10;
    wait for 20 ns;
    W_SHOW_TIME <= '1';
    wait for 20 ns;
    W_NO_PICS <= 20;
    wait for 20 ns;
    W_SHOW_TIME <= '0';
    wait for 20 ns;
    wait;
  end process;
end TEST;
  • The testbench is always the top
    level of the hierarchy, i.e. it does
    not have an interface to other
    modules

 
  • The device under test (DUT) has to
    be declared before it can be used
    in the architecture
 
  • The signals that are connected to
    the DUT need to be declared as
    well. All signals acting as DUT
    stimulus are also initialized.
 
  • Instantiation of the DUT


 
  • Stimulus process








 
  • Plain wait-statement:
    Stop process execution
configuration CFG_TB_DISP_MUX of
                  TB_DISP_MUX is
  for TEST
  end for;
end CFG_TB_DISP_MUX;
  • The default configuration may be
    used for the testbench as the com-
    ponent name of the DUT matches
    the entity name

 

3.1.3 Results

The waveform display shows that DISP_PHOTO always holds the current value of the selected input port. Changes to this value are transferred to the output immediately whereas modifications to the other port do not affect the output. Thus, the multiplexer behaves as specified.When inspecting the synthesized result, please note that the bus width for the data signals is 32 bit. This is because their data type was specified as integer without any range restrictions. Generally, omitting the range specification will result in a waste of resources. This is one of the reasons for a redesign of the multiplexer as next step.