2.5 VHDL Simulator
In order to verify the proper behaviour of your VHDL code, you will also need to create testbenches that stimulate your design. The testbench for the AND gate contains the instantiation of the device under test (DUT) and a simple stimulus process that assigns all possible signal combinations to the component inputs.
Please create the file tb_and_gate.vhd and enter the following VHDL code:
VHDL code of the testbench
library IEEE;
use IEEE.std_logic_1164.all;
entity TB_AND_GATE is
end TB_AND_GATE;
architecture TEST of TB_AND_GATE is
component AND_GATE
port (A, B : in std_logic;
Z : out std_logic);
end component;
signal W_A, W_B, W_Z : std_logic;
begin
DUT : AND_GATE
port map(A => W_A,
B => W_B,
Z => W_Z);
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STIMULI : process
begin
W_A <= '0';
W_B <= '0';
wait for 10 ns;
W_A <= '1';
wait for 10 ns;
W_B <= '1';
wait for 10 ns;
W_B <= '0';
wait for 10 ns;
wait;
end process STIMULI;
end TEST;
configuration CFG_TB_AND_GATE of
B_AND_GATE is
for TEST
end for;
end CFG_TB_AND_GATE;
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Prior to simulation you will also have to compile the file, i.e. please run the VHDL analyser (e.g. 'myanalyser and_gate.vhd'; or you have to select a menu entry, e.g. 'analyse').
Now you are ready to invoke the VHDL simulator if not already done. If not done automatically you have to choose the object to simulate and specify additional simulation parameters. Remember that the configuration is the only VHDL object that can be simulated. Some tools require no (top-) configuration as they built up a default configuration on their own. In this case you can select the top entity for simulation (here it would be TB_AND_GATE). In the other case please select CFG_TB_AND_GATE and press OK to open the simulation control window. The next points describe features which are common to most simulation tools:
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The source code currently simulated is shown in a window. Normally you can change the content of this window by moving up and down in the design hierarchy.
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In another window some status information (current hierarchy level, current simulation time, etc.) is given and there are a couple of short cut buttons for the most commonly used commands.
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Sometimes there is a command interface to the simulator, e.g. a command line at the very bottom of the display.
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Normally you can move your design hierarchy using commands or a design hierarchy browser. The design hierarchy is mostly presented like a filesystem (UNIX: '/' denotes the root of the hierarchy, '..' the previous level). In this example, the first hierarchy level contains your testbench (/TB_AND_GATE) and the referenced packages (/STD_LOGIC_1164 and /STANDARD), which is always loaded.
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In order to view the data in a waveform display, you will have to invoke the waveform display tool. Sometimes this is done automatically when you start the simulation. Please make sure that all signals of your testbench are being traced during simulation (refer to the user manual of the simulation software used).
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Simulation Control
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The actual simulation cycle is started with the a 'run' command (or button). If no additional options are given, the simulator normally stops when no signals need to be updated anymore. In this example, the simulator will stop after 40 ns.
Optionally, you may specify a maximum run time, e.g. 'run 100' to display the signal values for 100 ns.
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If you have for example a clocked design and want to simulate just one clock cycle at a time, it is convenient to enter the clock period as an argument of the 'run' command. Perhaps you have to fix the simulation step width in a menu entry.
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You may stop the simulation cycle either by setting breakpoints or with a manual interrupt. Of course, the simulation will also be stopped, if an VHDL assertion with the appropriate severity level is violated or if a runtime error occurs.
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There exist two breakpoint variants: The 'Stop at' function halts the execution when the corresponding VHDL code line is reached. Please note, however, that in this case probably not all signals carry their new values for the current time step. The 'Event Bkpt.' function enables you to interrupt the simulation whenever the selected signal changes its value.
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Once the simulation is stopped, you normally can proceed step wise via a 'step' and/or 'next' command.
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Normally the simulation tool creates a history (file) of the commands you entered. So you can repeat your simulation by loading this history.