1. Introduction

This VHDL teaching program is divided into several exercises. By writing typical VHDL programs you learn how to use this hardware description language. In the beginning you are guided in a step by step manner, later on when you are used to the language and the tools you will solve the tasks on your own. We are referring to the VHDL'87 standard, because the VHDL'93 is not yet supported by all tool manufacturers.

1.1 Structure of the Exercises

The tasks are divided into different sections:

1.2 Style Guide

In VHDL it is very important to have a consistent naming. The following naming conventions should be followed within this workshop:

 

Naming conventions

File name:

mydesign.vhd

for the VHDL file

Entity name:

MYDESIGN
TB_MYDESIGN

for the model
for the testbench

Architecture name:

RTL
TEST

for RTL code
for the architecture of the testbench

Configuration name:

CFG_TB_MYDESIGN

for the configuration of the testbench

Type definition name:

T_<TYPE_NAME>

a leading T_ ...