The design flow that will be followed throughout the exercises will be demonstrated at the example of a simple AND-gate. Please create a file named and_gate.vhd in your VHDL sources directory (~/workshop) and enter the following code.
Before you will be able to simulate the design you have to compile your ASCII sources. An so called analyser (sometimes also called "compiler", "reader", ...) is used for this purpose. The resulting files are stored in the default library which is mapped to the directory ./WORK in the simulation setup file. If you need to compile your sources into a different library, please refer to the corresponding user manual. Of course, the other library has to be mapped to a physical directory, as well.
Please remember that the VHDL design units have to be analysed in a certain order. You (sometimes the software will do this for you) will have to observe the following rules in order to avoid compilation errors:
The referenced standard package std_logic_1164 is already available in compiled format, i.e. you just have to analyse the entity AND_GATE before its RTL architecture. As the entity description is located in front of the architecture definition in the source code, please just compile this file and you will be ready to simulate the design.