3.10.1 Synopsis
A main control unit is needed to coordinate the actions of the different modules.
The interface of the module is depicted in the next drawing:
The main controller interface
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When the trigger button is pressed the shutter shall be opened and stay opened for the selected exposure time. This is done by setting the TIMER_GO signal one period to high, so the exposure controller opens the shutter for the selected exposure time. After the exposure time has passed the film has to be transported. So the motor needs a signal to start the transport Therefore MOTOR_GO is set to high for one period.
Now two things can appear: The motor has successfully transported the film, which is signalled by the MOTOR_READY signal. In this case a new photo can be made by the camera. It is the TRIGGER signal has to be examined again.
Or an error occurred while transporting the film. In this case the MOTOR_ERROR signal is set and the ERROR output signal has to be set, so the display indicate this case. When the cause of the error is removed (e.g. a new film is inserted) this has to be signalled by the user by pressing the trigger button.
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Behaviour:
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The current architecture will contain only one finite state machine. For that a combinational process, a clocked process and the concurrent output assignments are needed. In the clocked process the next state will be stored as the current state with every rising clock edge. Here the FlipFlops of the state machine are generated.
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In the combinational process the next state will be evaluated in a case statement depending of the current state and the input values of TRIGGER, EXPOSE, MOTOR_READY and MOTOR_ERROR.
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The output values are evaluated and assigned to the outputs in concurrent signal assignments. The expression in this assignment depend only on the current state and the relevant input signals. So a Moore machine has to be implemented!
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Data types:
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The main controller deals purely with control signals, i.e. only
std_ulogic
is used for the entity ports. Additionally, an internal signal is necessary to store the current controller state. You should define your
own enumeration type
for this purpose which holds all possible states of the finite state machine.
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To do:
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Create the new VHDL file.
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Write a testbench to verify the design. Use assertions to check the exposure times during the simulation run.
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Compile and simulate the design.
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Compare the number of Flip Flops that you would expect with the synthesis result.