2.6 VHDL Synthesis

After you have verified the function of your model with the simulator you can run the synthesis tool. Again you have to analyse the VHDL source code. This is normally done automatically when you read in your VHDL file.

In future tasks/exercises we will define our own packages. The synthesis tool requires that packages are read (analysed) before they are used or referenced. The most frequent errors with the synthesis are missing not read (analysed) packages!