9.1 Block

...
ENTITY e IS
    ...
BEGIN
    ...
END e ;

...
ARCHITECTURE a OF e IS
    ...
BEGIN
    ...
END a ;

...
CONFIGURATION c
        OF e IS
    ...
    ...
    ...
END


...
PACKAGE pkg IS
    ...
    ...
    ...
END pkg ;

block_statement ::=

block _label :
block [ ( guard _expression ) ] [ is ]
    block_header
    block_declarative_part
    begin
        block_statement_part
end block [ block _label ] ;


..
PACKAGE BODY pck
        IS
    ...
    ...
    ...
END pck ;

...
b: BLOCK IS
    ...
BEGIN
    ...
END BLOCK b ;

FUNCTION f (...)
    RETURN r IS
    ...
BEGIN
    ...
END f ;

PROCEDURE p (...) IS
    ...
BEGIN
    ...
END p ;

p : PROCESS
    ...
BEGIN
    ...
END PROCESS p ;

9.1.1 Further definitions

label ::= identifier

expression ::=
    relation { and relation }
    | relation { or relation }
    | relation { xor relation }
    | relation [ nand relation ]
    | relation [ nor relation ]

block_header ::=
    [ generic_clause
    [ generic_map_aspect ; ] ]
    [ port_clause
    [ port_map_aspect ; ] ]

block_declarative_part ::=
    { block_declarative_item }

block_statement_part ::=
    { concurrent_statement }

9.1.2 Examples

b : BLOCK
BEGIN
   s <= '1' AFTER 2 ns ;
END BLOCK b ;

This simple block has a label and a delayed signal
assignment in the statement part.

c : BLOCK
   SIGNAL int : bit_vector( 1 TO 3 )
                := "010" ;
BEGIN
   s <= int AFTER 5 ns ;
END BLOCK c ;


This block has an additional header in which the
signal int is declared.

latch : BLOCK ( clock = '1' )
BEGIN
   latch_output <= GUARDED
         latch_input AFTER 1 ns ;
END BLOCK latch ;

In this block a controlled signal assignment is used.
If the condition clock = '1' is not fulfilled the signal
assignment is not carried out.

lbl : BLOCK
   PORT ( a, b : INOUT bit ) ;
   PORT MAP ( a => s1, b => s2 ) ;
BEGIN
   b <= a AFTER 1 ns ;
   a <= b AFTER 1 ns ;
END BLOCK lbl ;



This block has separate in- and outputs which are
linked to the overriding signals by the PORT MAP .