3.5 STEP 5: A Decoder

3.5.1 Synopsis

The camera has a different button for each exposure time, i.e. the data signals from the keypad are transferred via a 10-bit data bus. If a button is pressed, the corresponding wire is set to 1.

The exposure times are calculated according to the following formula:

time(button) = 2^(-button), for button=0..9 (time in seconds).

The result (1/1 s, 1/2 s, 1/4 s, ..., 1/512 s) shall be shown on the 7-segment display. Thus, another decoder is needed. We will not introduce any new VHDL concepts in this exercise but suggest to try out different implementations and to observe their impact on the synthesis result.

The block diagram of the new module is rather simple.

 

The keypad decoder

 

3.5.2 Implementation

The decoder entity

library ieee;
use ieee.std_logic_1164.all;
use work.P_DISPLAY.all;

entity DECODER is
  port (KEYPAD : in  std_ulogic_vector
                           (9 downto 0);
        KEY : out T_DIGITS);
end DECODER;
  • The use-clause is only valid for the
    very next following design unit.
    However, it applies automatically
    to any secondary units, i.e. these
    statements need not to be repeated
    in the architecture files.
 

The decoder architecture based on a case-structure

architecture RTL_CASE of DECODER is
begin
  process(KEYPAD)
  begin
    case KEYPAD is
      when "1000000000" => KEY <= (5,1,2);
      when "0100000000" => KEY <= (2,5,6);
      when "0010000000" => KEY <= (1,2,8);
      when "0001000000" => KEY <= (0,6,4);
      when "0000100000" => KEY <= (0,3,2);
      when "0000010000" => KEY <= (0,1,6);
      when "0000001000" => KEY <= (0,0,8);
      when "0000000100" => KEY <= (0,0,4);
      when "0000000010" => KEY <= (0,0,2);
      when "0000000001" => KEY <= (0,0,1);
      when others       => KEY <= (0,0,0);
    end case;
  end process;
end RTL_CASE;
       
  • The input signal is a vector num-
    bered 9 downto 0. Thus, the signal
    which refers to button9 is the left-
    most signal of the data bus.
     
  • The input is decoded only if a sin-
    gle button is pressed. All other
    inputs are ignored.

 

 

The decoder architecture based on a if-elsif-structure

architecture RTL_IF of DECODER is
begin
  process(KEYPAD)
  begin
    if KEYPAD(0) = '1' then
      KEY <= (0,0,1);
    elsif KEYPAD(1) = '1' then
      KEY <= (0,0,2);
    elsif KEYPAD(2) = '1' then
      KEY <= (0,0,4);
    elsif KEYPAD(3) = '1' then
      KEY <= (0,0,8);
    elsif KEYPAD(4) = '1' then
      KEY <= (0,1,6);
    elsif KEYPAD(5) = '1' then
      KEY <= (0,3,2);
    elsif KEYPAD(6) = '1' then
      KEY <= (0,6,4);
    elsif KEYPAD(7) = '1' then
      KEY <= (1,2,8);
    elsif KEYPAD(8) = '1' then
      KEY <= (2,5,6);
    elsif KEYPAD(9) = '1' then
      KEY <= (5,1,2);
    else
      KEY <= (0,0,0);
    end if;
  end process;
end RTL_IF;
  • A different name is used for this
    architecture which makes it possi-
    ble to select the implementation
    via the VHDL configuration mech-
    anism.
  • This implementation defines a pri-
    ority for the buttons. The display
    value is generated as soon as a '1'
    is detected in the incoming signal.
    (0,0,0) appears only if none of the
    keys is pressed.
  • It is also possible to compare the
    entire KEYPAD signal with fixed
    values (if KEYPAD = "1000000000" ...)
    In this case, both architectures
    would show the same behaviour in
    simulation. The synthesis result
    will also be the same if the com-
    piler is able to detect that the
    conditions do not overlap.
 

The configuration for the decoder unit

configuration CFG_TB_DECODER of
                  TB_DECODER is
  for TEST
    for all : DECODER
      use entity work.DECODER(RTL_CASE);
      -- use entity work.DECODER(RTL_IF);
    end for;
  end for;
end CFG_TB_DECODER;
  • The configuration creates a simu-
    latable object and may be placed
    in a separate file
  • Here, the default configuration has
    been replaced with the VHDL
    code to switch between the two
    alternatives