3.6.1 Synopsis
When an exposure time is selected by the user it has to be stored. Edge-triggered Flip-Flops are used for this purpose. The contents of the register are updated only with the rising edge of the clock signal. This way, differences in the path delay become irrelevant as long as the maximum delay is shorter than the clock period.
In addition to the clock signal a second enabling condition is needed in this case. Valid exposure times shall be stored until another exposure time is selected. Only legal button combinations are mapped to display values other than (0,0,0) by the decoder, i.e. it is sufficient to exclude this value triple from being stored.
The reset input signal is necessary to be able to bring the chip into a defined state, e.g. after power-up.
The complete interface of the register is shown in the following figure:
The exposure time latch
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Behaviour:
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The reset shall be implemented asynchronously, i.e. a process with sensitivity list is the only viable option in this case. The following template for clocked processes has to be used:
if RESET
...
elsif RISING_CLOCK_EDGE
...
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After a rising clock edge has been detected it must be checked whether a key was pressed. If yes, the new exposure time is stored in the register.
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Data types:
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The exposure latch is used to store the exposure time, i.e.
T_DISPLAY
is the appropriate type for the data signals. CLK and RESET are single bit control signals and shall therefore be of type
std_ulogic
.
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To do:
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Write a new file with the VHDL description of the exposure latch.
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Write a testbench to verify the design. The periodic clock signal generation should be placed in a separate stimuli process!
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Compile and simulate the design.
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Synthesize the module.