configuration_specification ::= |
|||
component_specification ::=
instantiation_list :
component_
name
binding_indication ::=
[
use
entity_aspect ]
[ generic_map_aspect ]
[ port_map_aspect ]
In the generic map aspect an actual must be an expression or the reserved word OPEN .
In the port map aspect an actual must be a signal, an expression or the reserved word
OPEN
.
(In VHDL'87 only signals could be connected with input ports; in VHDL'93 globally static values can be used.)